The present invention relates to a method for estimating a yield In order to determine the number of non-defective devices to be obtained with respect to the number of charged wafers in manufacturing integrated circuit devices.
Generally, in devices for diversified small-quantity production in which new processes are often developed such as logic, microcomputer, and ASIC, if the number of produced non-defective devices does not reach the required number, it becomes a serious problem. This inevitably leads to the charging of a large number of wafers with a prescribed allowance, which has resulted in waste such as the production of a large number of non-defective devices exceeding the required number.
Therefore, on manufacturing integrated circuit devices from semiconductor wafers, it is an important problem to precisely estimate the number of non-defective devices to be finally obtained from the number of charged wafers, whereby the allowance of the number of wafers to be charged is reduced to implement a reduction in number of inutile wafers, and the savings in waste time and materials required for manufacturing thereof.
Thus, as a method for estimating the yield in the process for manufacturing integrated circuit devices, there has been a conventional method In which defect density in a diffusion process or the like Is employed. According to this method, the area of each chip In an integrated circuit, and the defect density in a diffusion fusion process or the like in which the integrated circuit devices are manufactured are used to calculate the expected yield of the integrated circuit devices. This method is effected, for example, by the procedure as follows:
If the chip area of an integrated circuit device is A (unit: cm.sup.2), and the defect density in the diffusion process used in the manufacturing thereof is D (unit: defects/cm.sup.2), the expected yield Y (unit: %)is calculated based on, for example, each equation as follows: EQU Y={exp(-A.times.D)}.times.100 (Poisson's equation) EQU Y={1/(1+A.times.D)}.times.100 (Seeds' equation) EQU Y=1/{(1+A.times.D.times.S).sup.1/S }.times.100 (Stapper's equation)
(where S stands for allowable process variation) EQU Y=[{(1-exp(-A.times.D)}/(A.times.D)].sup.2.times.100 (Murphy's equation) EQU Y=exp{- (A.times.D)}.times.100 (Moore's equation)
Here, the defect denotes a point defect such as pinhole in an oxide film, mask defect, contamination, or crystal defect.
The aforementioned Poisson's equation is calculated from the following procedure.
For the probability of defect generation occurring in a large number of manufacturing processes, the binomial distribution representing the probability P that x defects occur is calculated based on the assumption that events each in their respective process are mutually independent, and assuming that the number of processes is sufficiently large, the probability of defect generation is sufficiently small, and defects are uniformly distributed within the wafer surface, among wafers, and from batch to batch, the defect density D becomes a constant. Accordingly, the probability P can be expressed as the following Poisson distribution: EQU P{X=x}={(A.times.D).sup.x /x!}exp(-A.times.D)
Therefore, the yield Y can be expressed as the following Poisson's equation: EQU Y=P{X=0}={exp(-A.times.D)}.times.100
Generally, however, it is said that the yield calculated according to the Poisson's equation tends to be smaller than the actual yield.
On the other hand, by supposing that the mean value A.times.D in the above Poisson distribution has a distribution, and that this distribution function is the Gamma function, the following Stapper's equation can be obtained: EQU Y=1/{(1+A.times.D.times.S).sup.1/S }.times.100
Assuming that S=1 in the above Stapper's equation yields the following Seeds' equation:
Y={1/(1+A.times.D)}.times.100
Therefore, this Seeds' equation is supposed to be included in the Stapper's equation in a broad sense. In the description below, the Seeds' equation is taken as the specific case of Stapper's equation, and hence it is decided that these equations are generically referred to as Stapper's equation.
Thus, in the conventional method, the expected yield has been estimated using each of the above estimation equations to determine the number of wafers to be charged based on the estimated result, thereby avoiding the consumption of inutile wafers, processing time and materials as much as possible.
However, when the yield is estimated using each of the above conventional equations, there has been a problem as follows: in the case where the chip area is small, or the number of masking is small, the estimated yield is relatively in fair agreement with the actual yield, whereas an increase in chip area causes a large deviation from the actual value. FIG. 7 is a characteristic curve showing the chip area dependence of the yield in each of the above equations. This indicates as follows: Poisson's equation, Stapper's equation (Seeds' equation), and Murphy's equation exhibit mutually close values of the expected yield, when the chip area is small. However, an increase in chip area causes the values to differ widely from one another. It is also predicted from the shape of the characteristic curve that an increase in chip area will cause an increase in discrepancy between an estimate and actual value.
As one example, comparison between estimates and actual values will be made below when yields are estimated using the above Stapper's equation, where it is assumed that S=1.
In the diffusion process where for defect density, D=0.63 (unit: defects/cm.sup.2), the case where the following integrated circuit devices A to C of various kinds are manufactured will be considered.
Integrated circuit device A Chip area 0.44 (unit: cm.sup.2)
Integrated circuit device B Chip area 0.79 (unit: cm.sup.2)
Integrated circuit device C Chip area 0.30 (unit: cm.sup.2)
For each of the above integrated circuit devices A to C, the above Stapper's equation is used to calculate the expected yield, leading to the following results:
Integrated circuit device A EQU Expected yield Ya1={1/(1+0.44.times.0.63}.times.100=78.3%
Integrated circuit device B EQU Expected yield Yb1={1/(1+0.79.times.0.63}.times.100=66.8%
Integrated circuit device C EQU Expected yield Yc1={1/(1+0.30.times.0.63}.times.100=84.1%
FIG. 5 shows a chip area dependence curve y1 of the expected yield when calculated by the use of Stapper's equation which is one example of the conventional calculation method described above, and the yields Za1 to Zc1 when the above integrated circuit devices A to C were actually manufactured. As shown in the same diagram, the actual yields Za1 to Zc1 are not in agreement with the estimate curve y1 based on Stapper's equation, and vary vertically across the curve y1.
Therefore, in conventional estimation of yields, wafers cannot help being charged with considerably large allowance even if any of the estimation equations are used, and hence there has been a difficulty in saving wasteful wafers, time, and the like.
Especially, in integrated circuit devices with short product life, the number of required wafers must be predicted already in the development stage thereof. However, there have occurred a large number of integrated circuit devices largely deviating from the expected yield.
Thus, the inventors of the present invention have made attempts to clarify the cause resulting in the aforementioned discrepancy between the estimates and actual values as shown in FIG. 5, and to attain the solution thereof. As a result, they have found that the main cause thereof seems to be attributable to a difference in density between elements such as transistor mounted in an integrated circuit device.